hello I'm Gary Sims from Andhra Thoris
and I've been locked exciting
announcements from armed this week we've
got more details on its new SOC
architecture called dynamic we've got
details about the new high-performance
core the core tech a 75 we also have
learned more about the new power
efficiency core the core is a 55 and
then of course it's the new GPU the mali
g72 so my plan is that they said I'm
going to do four different videos for
you
they're going to be shortened to the
point in each one is going to
concentrate on each of these four
announcements so the first day is going
to be about dynamic so the question
before us is is what is dynamic and how
will it affect SOC design in the future
well let me explain so first let's start
with a bit of history now one of the
biggest changes we've seen in mobile
processors over the last recent years is
the use of heterogeneous
multi-processing now that means that in
a heterogeneous environment not all the
cores inside the processor are the same
now typically nowadays in an octa-core
processor those before high-performance
cause that's a core tech a 73 or 48 72
and then they're before power efficient
core that say the cortex a53 now these
groups of cores were put into different
clusters so you had a cluster or four
high a performance course and in a
separate cluster or for energy-efficient
cause and originally the design work you
could actually just switch between them
so it was either running for one type or
for the other type and that's actually
what our app will do in the 18 fusion
today but on the other processors from
Samsung on Qualcomm and Huawei things
have developed quite significantly
we're now in a stage we can run all
eight cores or six cores simultaneously
and the prep or all of them are being
used at the same time and jobs are moved
from one core to the other according to
the energy requirements needed now the
promise designs these classes are quite
independent so for example across a
cluster you might have a level two cache
and across the other class you might
have a level two cache but they didn't
share a cache and so therefore the
indicate had to be really clever to make
sure that the information in the caches
was kind of spread amongst both
sets of classism and basically because
there was kind of semi-autonomous when
it that created barriers whenever
there's a barrier between something that
reduces performance and so armor been
thinking now for about three years how
could you make a SOC where there were
different types of cause but inside the
same cluster which means they could
share a lot of the same resources they
could share the same cache it would make
the interconnect less complicated and of
course it would increase performance and
that's what dynamic is they can't the
solution that allows SOC manufacturers
to produce anything up to an optical
processor mixing and matching different
types of high performance and energy
efficient cause inside one cluster now
the ramifications of this are some
really quite significant first of all
it's now much easier for an SOC maker to
produce an octa-core processor before
they had to have the two clusters are
complicated interconnect but now inside
one cluster you can just pick and match
which of the calls you want to put into
that cluster and in fact arm say there
are now up to three thousand different
configurations that you can make inside
a processor using dynamic and that of
course includes what cores to use also
what levels of caching to you what
components to include in terms of
floating-point and neon and all that
inside of a different cause there really
a whole bunch of different
configurations that's great for us as
consumers because it means actually
there will be a whole bunch of different
different shading types of CPU so if
maybe one company take Alcorn want to go
one direction maybe while we want to go
to another direction maybe some some
will take it in another direction there
are just so many different ways and each
company will have its unique proposition
that why its processor design is maybe
better which because as a configuration
is better than a different one now up
until now and we've really seen HMP
processes they've really been two plus
four or four plus four so all of the
current flagship SOC they're using for
high-end cause that's cortex a seventy
three for example and then for power
efficient cause that's a the cortex a53
and we've had some hexa-core process
before where there were two high
performance cause and
or power efficiency cause but now in
with this new system in dynamic we can
see that whole thing mixed up for
example you might see a 4 and a 1 or you
might see a 3 in a 1 or you might see a
7 and a 1 I mean the combinations are
anything you like inside of that one
cluster up to a processor calls now why
they important it means that SOC makers
particularly those that are making for
the mid and low range can now mix and
match much easier what types of cause
they want to put inside their process
and because it's all about silicon size
when it comes to pricing when it comes
to profit or about how much silicon is
used inside of each of these processors
now maybe a mid-range processor might
just have one how high performance core
would you do this great single trading
performance great scores on Geekbench on
the single threaded performance and a
great score user experience because some
types of tasks really do heavily use one
single core but then they were still
before power efficiency calls for all of
those other like work that needs to go
on and yet that would be maybe less
silicon size and maybe an octa-core
processor that was just using cortex a53
across the board so that actually means
we can see quite a lot of
differentiation occurring now in the
mid-range now I'm pretty sure that at
the high end we're still going to see
four plus four as the norm but there is
room for experimentation maybe we'll see
five plus three or maybe we'll see six
plus two I mean these processor makers
now can really start to think about
different combinations they want to make
and see what comes out better in terms
of performance and in terms of energy
efficiency and we might see quite some
diverse different solutions coming from
the big SOC makers and the other big
difference is for the first time now in
an are mobile based processor we have l3
cache and if you don't know what else
recache is I really recommend you go and
watch my video what is cache memory gary
explains and there you'll see all about
l1 l2 and l3 cache now up until now the
l2 cache has been shared across the
cluster the l1 cache was on a per CPU
core basis and there was no l3 cache now
if I now make you've got an l1 cache
that is per
CPU core and l2 cache which is per CPU
core and then an l3 cache which is
across the entire cluster now if you're
thinking that would actually raise the
silicon cost because now you would have
an l1 l2 and l3 cache it actually turns
out that actually the l1 the l2 cache
are very much smaller than they were
before because now the l3 cache is up to
4 megabytes now in implementing this l3
cache are more than a really clever
thing the SOC maker is allowed to
partition the cache into different
sections and that's good for two reasons
one it stops what they call cache
thrashing where one particular part of
the SOC is dominating the cache because
it's shared across all of the CPU cores
but also because of this partitioning
they can shut down parts of the cache
and therefore save power so when a
particular core powers down if it's the
only core using a particular part of the
cache then that part of the cache can
power down in fact there are even
scenarios where you might not even our
up the cache for certain operations only
later on you might power that were you
when you need it and actually that's all
controlled in the software a one last
thing worth means because all the CPU
cores are now inside of the same cluster
powering down those CPU cores so they
are switched off and therefore not using
any power not draining your battery at
all is much easier than it was before
in fact the number of steps required
internally to do that has been halved
and before it was mainly handled by the
software inside of it saved within its
kernel but now actually it's all handled
in Hardware which means of course it is
super efficient sort of this means for
us as consumers but I think in 2018
we're going to see phones using
processes based on the dynamic
architecture I think we're going to see
them from Qualcomm and Samsung and
Huawei and from mediatek now how they
choose to do that of course we don't yet
know I have a feeling that certainly in
the mid-range we're going to see
Qualcomm processors using dynamic we're
certainly see processors from media tech
using dynamic maybe at Qualcomm we'll
continue with their cryo series using
the built on court
a license so they'll take this dynamic
they'll take the a 7500 take the 855 and
they will modify it to make a custom
semi custom processor it's unknown what
Samson and I do because they've got the
m1 and the m2 cause and I don't know how
they going to get to integrate that with
dynamic so it can be interesting to see
what they do in the future and I think
while we are going to basically do what
they've done for their last current
generation they're going to take four
cortex 875 calls and four cortex 855
calls and they're going to put them into
a big beefy queueing processor with a
Mali g72 GPUs this is my speculation
we'll see what happens so to recap
dynamic is a new way of building mobile
proteins based on the ARM architecture
it's coming in the with the cortex a 75
it's coming with the court it's a 55
it'll be mine next videos it brings all
of these core up to an optical into one
cluster you've now got a level three
cache which boosts performance and they
and makes it more energy efficient and
of course those are the things that we
want i'm garrison for my under authority
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